Concatenation between two signals

Allow a signal of an io Bundle to be directionless.

Allow a signal to be overridden.

Allow a register to be partially assigned

Allow a register to have only an init (no assignments)

Cast signal to Bits

Set a signal as inout

Set a data as input

Set a data as output

Assign the bundle with an other bundle by name

Assign all possible signal fo the bundle with an other bundle by name

for interface find modport

Flip the direction of the signal.

in and out are swapped, inout stay the same.

For a register, get the value it will have at the next clock, as a combinational signal.

Return the width of the data

Get current component with all parents

Create a signal set to 0

Put the combinatorial logic driving this signal in a separate process

Disable combinatorial loop checking for this Data

Pull a signal to the top level (use for debugging)

Useful for register that doesn't need a reset value in RTL, but need a random value for simulation (avoid x-propagation)

Return a version of the signal which is allowed to be automatically resized where needed.

The resize operation is deferred until the point of assignment later. The resize may widen or truncate, retaining the LSB.

root interface

Set baseType to Combinatorial

Remove the direction (in, out, inout) to a signal

Set baseType to reg

Recursively set baseType to reg only for output

Generate this if condition is true