Generate prefixes from values of this type in the Chisel compiler plugin

Users can mixin this trait to tell the Chisel compiler plugin to include the names of vals of this type when generating prefixes for naming Data and Mem instances. This is generally useful whenever creating a class that contains Data, Mem, or Module instances but does not itself extend Data or Module.

Data type for representing bidirectional bitvectors of a given width

Analog support is limited to allowing wiring up of Verilog BlackBoxes with bidirectional (inout) pins. There is currently no support for reading or writing of Analog types within Chisel code.

Given that Analog is bidirectional, it is illegal to assign a direction to any Analog type. It is legal to "flip" the direction (since Analog can be a member of aggregate types) which has no effect.

Analog types are generally connected using the bidirectional attach mechanism, but also support limited bulkconnect <>. Analog types are only allowed to be bulk connected *once* in a given module. This is to prevent any surprising consequences of last connect semantics.

Interface for Annotations in Chisel

Defines a conversion to a corresponding FIRRTL Annotation

Enhanced interface for Annotations in Chisel

Defines a conversion to corresponding FIRRTL Annotation(s)

Enforces that A is a Chisel subtype of B.

A is a Chisel subtype of B if A contains all of B's fields (same names and same types). Only public fields that are subtypes of chisel3.Data are considered when checking for containment.

In the following example A is a Chisel subtype of B:

class A extends Bundle {
  val x = UInt(3.W)
  val y = UInt(3.W)
  val z = UInt(3.W)
}
class B extends Bundle {
  val x = UInt(3.W)
  val y = UInt(3.W)
}

Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

A variant of BlackBox, this has a more consistent naming scheme in allowing multiple top-level IO and does not drop the top prefix.

Data equivalent of Scala's scala.Tuple9

Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple9 in chisel3.experimental.conversions

Data equivalent of Scala's scala.Tuple2

Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple2 in chisel3.experimental.conversions

Data equivalent of Scala's scala.Tuple3

Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple3 in chisel3.experimental.conversions

Data equivalent of Scala's scala.Tuple4

Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple4 in chisel3.experimental.conversions

Data equivalent of Scala's scala.Tuple5

Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple5 in chisel3.experimental.conversions

Data equivalent of Scala's scala.Tuple6

Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple6 in chisel3.experimental.conversions

Data equivalent of Scala's scala.Tuple7

Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple7 in chisel3.experimental.conversions

Data equivalent of Scala's scala.Tuple8

Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple8 in chisel3.experimental.conversions

Data equivalent of Scala's scala.Tuple9

Users may not instantiate this class directly. Instead they should use the implicit conversion from Tuple9 in chisel3.experimental.conversions

Indicates if this Record represents an "Opaque Type"

Opaque types provide a mechanism for user-defined types that do not impose any "boxing" overhead in the emitted FIRRTL and Verilog. You can think about an opaque type Record as a box around a single element that only exists at Chisel elaboration time. Put another way, if this trait is mixed into a Record, the Record may only contain a single element with an empty name and there will be no _ in the name for that element in the emitted Verilog.

Mixin this trait to let chisel auto serialize module, it has these constraints: 1. Module should not be any inner class of other class, since serializing outer class is impossible. 2. Module should have and only have one parameter with type T:

class FooSerializableModule[FooSerializableModuleParameter](val parameter: FooSerializableModuleParameter)

3. user should guarantee the module is reproducible on their own.

the serializable module generator:

Parameter for SerializableModule, it should be serializable via upickle API. For more information, please refer to https://com-lihaoyi.github.io/upickle/

Indicates that the compiler plugin should generate cloneType for this type

All user-defined Records should mix this trait in as it will be required for upgrading to Chisel 3.6.

A sealed class representing a fixed point number that has a bit width and a binary point The width and binary point may be inferred.

IMPORTANT: The API provided here is experimental and may change in the future.

Chisel types that have binary points support retrieving literal values as Double or BigDecimal

A sealed class representing a fixed point number that has a range, an additional parameter that can determine a minimum and maximum supported value. The range can be used to reduce the required widths particularly in primitive operations with other Intervals, the canonical example being

val one = 1.I
val six = Seq.fill(6)(one).reduce(_ + _)

A UInt computed in this way would require a Width binary point The width and binary point may be inferred.

IMPORTANT: The API provided here is experimental and may change in the future.